The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Dec. 31, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

William C. Hasenplaugh, Boston, MA (US);

Tryggve Fossum, Northborough, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 9/50 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 1/3243 (2013.01); G06F 9/5094 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 9/3885 (2013.01);
Abstract

A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores.


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