The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2016
Filed:
Jul. 31, 2013
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Ting-Wei Chiang, New Taipei, TW;
Chun-Fu Chen, Chiayi, TW;
Hsiang-Jen Tseng, Hsinchu, TW;
Wei-Yu Chen, Hsinchu, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Shang-Chih Hsieh, Yangmei, TW;
Li-Chun Tien, Tainan, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.