The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2016
Filed:
Oct. 28, 2013
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chen-Hua Tsai, Hsinchu County, TW;
Jian-Cheng Chen, New Taipei, TW;
Chin-Yueh Tsai, Taichung, TW;
Yao-Jen Fan, Chiayi, TW;
Heng-Kun Chen, Tainan, TW;
Hsiang Yang, Hsinchu County, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/36 (2012.01); H01L 23/48 (2006.01); G06F 17/50 (2006.01); G03F 1/70 (2012.01);
U.S. Cl.
CPC ...
H01L 23/48 (2013.01); G03F 1/70 (2013.01); G06F 17/5072 (2013.01); H01L 23/481 (2013.01); G06F 2217/12 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.