The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Sep. 06, 2013
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Nian Niles Yang, Mountain View, CA (US);

Chris Avila, Saratoga, CA (US);

Steven Sprouse, San Jose, CA (US);

Alexandra Bauche, San Jose, CA (US);

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/3427 (2013.01); G11C 16/3459 (2013.01);
Abstract

Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.


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