The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Jun. 24, 2014
Applicant:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Inventors:

Won-Kyung Park, Seoul, KR;

Ki-Jae Hur, Seoul, KR;

Hyeong-Sun Hong, Gyeonggi-do, KR;

Se-Young Kim, Gyeonggi-do, KR;

Jun-Hee Lim, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/108 (2006.01); H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10897 (2013.01); H01L 21/265 (2013.01); H01L 21/28158 (2013.01); H01L 27/10894 (2013.01); H01L 29/0649 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01);
Abstract

A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.


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