The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Apr. 15, 2009
Applicants:

Reinhard Schauer, Laufen, DE;

Christian Hager, Kastl, DE;

Inventors:

Reinhard Schauer, Laufen, DE;

Christian Hager, Kastl, DE;

Assignee:

SILTRONIC AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/324 (2006.01); H01L 21/02 (2006.01); C30B 33/02 (2006.01); C30B 25/02 (2006.01); C30B 25/10 (2006.01); C30B 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02532 (2013.01); C30B 25/02 (2013.01); C30B 25/10 (2013.01); C30B 29/06 (2013.01); C30B 33/02 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02664 (2013.01); H01L 21/324 (2013.01);
Abstract

Epitaxially coated semiconductor wafers are prepared by a process in which a semiconductor wafer polished at least on its front side is placed on a susceptor in a single-wafer epitaxy reactor and epitaxially coated on its polished front side at temperatures of 1000-1200° C., wherein, after coating, the semiconductor wafer is cooled in the temperature range from 1200° C. to 900° C. at a rate of less than 5° C. per second. In a second method for producing an epitaxially coated wafer, the wafer is placed on a susceptor in the epitaxy reactor and epitaxially coated on its polished front side at a deposition temperature of 1000-1200° C., and after coating, and while still at the deposition temperature, the wafer is raised for 1-60 seconds to break connections between susceptor and wafer produced by deposited semiconductor material before the wafer is cooled.


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