The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Apr. 02, 2014
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Subramanian B. Chebiyam, Sunnyvale, CA (US);

Santosh Kulkarni, Bangalore, IN;

Anshuman Chandra, Sunnyvale, CA (US);

Rohit Kapur, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G01R 31/318547 (2013.01);
Abstract

A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.


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