Transceiver clock architecture with transmit pll and receive slave delay lines

Abstract

A method and apparatus for transceiver clock architecture with transmit PLL and receive slave delay lines. In one embodiment, the method includes the generation of a transmitter (Tx) clock signal by adjusting a control voltage of a voltage controlled oscillator to lock a phase and frequency of Tx clock signal to a reference clock signal. In one embodiment, a frequency of the Tx clock signal is a multiple of a frequency of the reference clock signal. In one embodiment, a slave delay line may be used, including a plurality of variable delay buffers that are configured according to the control voltage to generate a receiver (Rx) clock signal in response to a received clock signal that is synchronized with the reference clock signal. The Rx clock signal may be provided to data recovery logic to sample data. Other embodiments are described and claimed.