The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 2016
Filed:
Aug. 23, 2012
Toshio Kawahara, Aichi, JP;
Kazumasa Okamoto, Hokkaido, JP;
Kazuhiko Matsumoto, Osaka, JP;
Risa Utsunomiya, Kyoto, JP;
Teruaki Matsuba, Kyoto, JP;
Hitoshi Matsumoto, Kyoto, JP;
Toshio Kawahara, Aichi, JP;
Kazumasa Okamoto, Hokkaido, JP;
Kazuhiko Matsumoto, Osaka, JP;
Risa Utsunomiya, Kyoto, JP;
Teruaki Matsuba, Kyoto, JP;
Hitoshi Matsumoto, Kyoto, JP;
CHUBU UNIVERSITY EDUCATIONAL FOUNDATION, Aichi, JP;
NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY, Hokkaido, JP;
OSAKA UNIVERSITY, Osaka, JP;
NISSIN ELECTRIC CO., LTD., Kyoto, JP;
Abstract
A thin film transistor is equipped with a silicon substrate, a channel layer, a source electrode and a drain electrode. The channel layer, the source electrode and the drain electrode are arranged on the main surface of the silicon substrate. The channel layer is composed of multiple carbon nanowall thin films, wherein the multiple carbon nanowall thin films are arranged in parallel to each other between the source electrode and the drain electrode, one end of each of the multiple carbon nanowall thin films is in contact with the source electrode, and the other end of each of the multiple carbon nanowall thin films is in contact with the drain electrode. An insulating film and a gate electrode are arranged on the rear surface side of the silicon substrate.