The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 2016
Filed:
Mar. 05, 2013
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Kazuhide Doi, Kanagawa, JP;
Soichi Homma, Kanagawa, JP;
Katsuyoshi Watanabe, Kanagawa, JP;
Taku Nishiyama, Kanagawa, JP;
Takeshi Ikuta, Kanagawa, JP;
Naohisa Okumura, Kanagawa, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01); G06K 19/077 (2006.01);
U.S. Cl.
CPC ...
H01L 23/495 (2013.01); G06K 19/07732 (2013.01); H01L 21/0201 (2013.01); H01L 23/3107 (2013.01); H01L 23/49551 (2013.01); H01L 23/49558 (2013.01); H01L 23/49575 (2013.01); H01L 23/49589 (2013.01); H01L 24/80 (2013.01); H01L 24/05 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05664 (2013.01); H01L 2224/451 (2013.01); H01L 2224/4813 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/48465 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19107 (2013.01);
Abstract
A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.