The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Jul. 24, 2014
Applicant:

Sandisk 3d, Llc, Milpitas, CA (US);

Inventors:

Tianhong Yan, Saratoga, CA (US);

George Samachisa, San Jose, CA (US);

Tz-yi Liu, Palo Alto, CA (US);

Tim Chen, Milpitas, CA (US);

Perumal Ratnam, Fremont, CA (US);

Assignee:

SANDISK 3D LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 27/06 (2006.01); H01L 45/00 (2006.01); G11C 7/18 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/0023 (2013.01); H01L 27/0688 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1266 (2013.01); H01L 45/142 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01); H01L 45/1608 (2013.01); G11C 7/18 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0083 (2013.01); G11C 2207/005 (2013.01); G11C 2213/15 (2013.01); G11C 2213/71 (2013.01); G11C 2213/77 (2013.01); G11C 2213/79 (2013.01); H01L 27/101 (2013.01);
Abstract

A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an 'on' condition for the double gated vertically oriented select devices to be activated.


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