The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Sep. 18, 2014
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Elan Banin, Raanana, IL;

Rotem Banin, Pardes-Hana, IL;

Ofir Degani, Haifa, IL;

Ran Shimon, Ramat Gan, IL;

Ashoke Ravi, Hillsboro, OR (US);

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/08 (2006.01); G04F 10/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); G04F 10/005 (2013.01);
Abstract

A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.


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