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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9230968 B1

PDFFull Text
Date of Patent:
Jan. 05, 2016

Filed:

Dec. 12, 2014

Methods of forming memory arrays and semiconductor constructions

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jaydip Guha, Boise, ID (US);

Shyam Surthi, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Wells St. John P.S.

Primary Examiner:

Christine Enad

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/102 (2006.01); H01L 27/105 (2006.01); H01L 21/8222 (2006.01); H01L 21/8229 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 27/08 (2006.01); H01L 27/082 (2006.01); H01L 29/732 (2006.01); H01L 29/868 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10876 (2013.01); H01L 21/0257 (2013.01); H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/8222 (2013.01); H01L 21/8229 (2013.01); H01L 21/823487 (2013.01); H01L 27/1021 (2013.01); H01L 27/1022 (2013.01); H01L 27/1052 (2013.01); H01L 27/1085 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H01L 29/6609 (2013.01); H01L 29/66272 (2013.01); H01L 29/66666 (2013.01); H01L 27/0814 (2013.01); H01L 27/0823 (2013.01); H01L 29/732 (2013.01); H01L 29/868 (2013.01);
Abstract

Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.

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