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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9230963 B1

PDFFull Text
Date of Patent:
Jan. 05, 2016

Filed:

Jan. 27, 2015

Semiconductor device with dual work function gate stacks and method for fabricating the same

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Yun-Hyuck Ji, Gyeonggi-do, KR;

Se-Aug Jang, Gyeonggi-do, KR;

Seung-Mi Lee, Gyeonggi-do, KR;

Hyung-Chul Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T Group LLP

Primary Examiner:

Brook Kebede

Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/28088 (2013.01); H01L 21/823842 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/78 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.

Find Patent Forward Citations

Ji, Yun-Hyuck. (2016). Semiconductor device with dual work function gate stacks and method for fabricating the same (U.S. Patent No. 9230963). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9230963

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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