The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2016
Filed:
Oct. 17, 2013
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01); H01L 21/22 (2006.01); H01L 21/38 (2006.01); H01L 21/44 (2006.01); H01L 21/302 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/0273 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76879 (2013.01);
Abstract
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.