The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Nov. 30, 2012
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ching-Wei Wu, Caotun Town, TW;

Chia-Cheng Chen, Taichung, TW;

Kuang Ting Chen, Taipei, TW;

Wei-Shuo Kao, Taichuang, TW;

Jui-Che Tsai, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/16 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/1039 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 8/16 (2013.01);
Abstract

A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.


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