The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2016
Filed:
Dec. 23, 2011
Applicants:
Andre Schaefer, Braunschweig, DE;
Ruchir Saraswat, Swindon, GB;
Inventors:
Andre Schaefer, Braunschweig, DE;
Ruchir Saraswat, Swindon, GB;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 7/00 (2006.01); G11C 11/4074 (2006.01); G11C 5/02 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/00 (2013.01); G11C 5/025 (2013.01); G11C 5/147 (2013.01); G11C 11/4074 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/15311 (2013.01);
Abstract
Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.