The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Feb. 25, 2013
Applicant:

Lattice Semiconductor Corporation, Portland, OR (US);

Inventors:

Daekyeung Kim, Palo Alto, CA (US);

Daeyun Shim, Saratoga, CA (US);

Baegin Sung, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/02 (2006.01); G09G 5/00 (2006.01); H04L 7/00 (2006.01); H04L 25/49 (2006.01);
U.S. Cl.
CPC ...
G09G 5/006 (2013.01); H04L 7/0008 (2013.01); H04L 25/49 (2013.01); G09G 5/008 (2013.01); G09G 2370/12 (2013.01);
Abstract

Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential data signal pair with a first clock signal of a differential clock signal pair. The encoder logic further generates a second signal pair, including encoding a second differential data signal pair with a second clock signal of the same differential clock signal pair. In another embodiment, decoder logic receives and decodes the first signal pair and the second signal pair, wherein the decoding generates the first differential data signal pair, the second differential data signal pair and a clock signal.


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