The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Dec. 06, 2013
Applicant:

Elite Semiconductor Memory Technology Inc., Hsinchu, TW;

Inventor:

Min-Chung Chou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G11C 29/48 (2006.01); G11C 29/26 (2006.01); G11C 29/00 (2006.01); G11C 29/56 (2006.01); G11C 29/12 (2006.01); G11C 29/40 (2006.01); G11C 29/10 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31912 (2013.01); G11C 29/00 (2013.01); G11C 29/10 (2013.01); G11C 29/1201 (2013.01); G11C 29/26 (2013.01); G11C 29/36 (2013.01); G11C 29/40 (2013.01); G11C 29/48 (2013.01); G11C 2029/5602 (2013.01);
Abstract

An exemplary embodiment of the present disclosure illustrates a memory test system comprising a memory device, a probe card, and a tester. The memory device comprises a memory die with a plurality of memory banks, a plurality of input circuits, and a plurality of output circuits, wherein each of the input circuits has a first input pin and a second pin, the first input pins of the input circuits are used to read a plurality of patches of data stored in memory cells of the memory banks, and the second input pins are used to receive a compressed result. The output circuits receive compressed signals output from the input circuits, and the probe card mixes the compressed output signals output from the output circuits to output a mixed compressed output signal to the tester.


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