The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2016
Filed:
Sep. 28, 2011
Keith A. Bowman, Hillsboro, OR (US);
Carlos Tokunaga, Hillsboro, OR (US);
James W. Tschanz, Portland, OR (US);
Keith A. Bowman, Hillsboro, OR (US);
Carlos Tokunaga, Hillsboro, OR (US);
James W. Tschanz, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single-transition DC-stressed path delay; and therefore enables the adjustment of the frequency of the dock signal to correspond to an amount or effect of the delay.