The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Apr. 08, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Wenfeng Zhang, San Jose, CA (US);

Parag Upadhyaya, Los Gatos, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018514 (2013.01); H03K 19/09432 (2013.01);
Abstract

A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.


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