The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Aug. 02, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yun-Chung Na, Hsinchu, TW;

Han-Din Liu, Santa Clara, CA (US);

Yimin Kang, San Jose, CA (US);

Shu-Lu Chen, Foster City, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/06 (2006.01); H01L 31/0216 (2014.01); H01L 31/107 (2006.01); H01L 31/0224 (2006.01); H01L 31/028 (2006.01); H01L 31/0232 (2014.01); H01L 31/108 (2006.01); H01L 31/18 (2006.01); H04B 10/60 (2013.01);
U.S. Cl.
CPC ...
H01L 31/02161 (2013.01); H01L 31/028 (2013.01); H01L 31/02327 (2013.01); H01L 31/022408 (2013.01); H01L 31/107 (2013.01); H01L 31/1085 (2013.01); H01L 31/1868 (2013.01); H01L 31/1872 (2013.01); H04B 10/60 (2013.01);
Abstract

A low voltage photodetector structure including a semiconductor device layer, which may be Ge, is disposed over a substrate semiconductor, which may be Si, for example within a portion of a waveguide extending laterally within a photonic integrated circuit (PIC) chip. In exemplary embodiments where the device layer is formed over an insulator layer, the insulator layer is removed to expose a surface of the semiconductor device layer and a passivation material formed as a replacement for the insulator layer within high field regions. In further embodiments, controlled avalanche gain is achieved by spacing electrodes in a metal-semiconductor-metal (MSM) architecture, or complementary doped regions in a p-i-n architecture, to provide a field strength sufficient for impact ionization over a distance not significantly more than an order of magnitude greater than the distance that a carrier must travel so as to acquire sufficient energy for impact ionization.


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