The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Dec. 10, 2010
Applicants:

Kenneth P. Snowdon, Cumberland, ME (US);

William Robert Newberry, Cumberland, ME (US);

James Hall, Cumberland, ME (US);

Roy Yarbrough, Cumberland, ME (US);

Inventors:

Kenneth P. Snowdon, Cumberland, ME (US);

William Robert Newberry, Cumberland, ME (US);

James Hall, Cumberland, ME (US);

Roy Yarbrough, Cumberland, ME (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01H 37/76 (2006.01); H01H 85/46 (2006.01); G01R 31/07 (2006.01);
U.S. Cl.
CPC ...
H01H 85/46 (2013.01); G01R 31/07 (2013.01); H01H 2085/466 (2013.01);
Abstract

Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.


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