The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2015
Filed:
Oct. 02, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chin-Hsiung Hsu, Guanyin Township, TW;
Chin-Chang Hsu, Banqiao, TW;
Yuan-Te Hou, Hsinchu, TW;
Godina Ho, Hsinchu, TW;
Wen-Hao Chen, Hsin-Chu, TW;
Wen-Ju Yang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.