The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Mar. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mauricio Breternitz, Austin, TX (US);

Youfeng Wu, Palo Alto, CA (US);

Peter Sassone, Austin, TX (US);

James Mason, Austin, TX (US);

Aashish Phansalkar, Austin, TX (US);

Balaji Vijayan, Austin, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 12/08 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 9/30 (2013.01); G06F 9/30152 (2013.01); G06F 9/3802 (2013.01); G06F 9/3816 (2013.01); G06F 12/0886 (2013.01); G06F 9/3822 (2013.01); G06F 9/3842 (2013.01);
Abstract

A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.


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