The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Sep. 26, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Girish Venkatasubramanian, Sunnyvale, CA (US);

Chaitanya Mangla, San Francisco, CA (US);

Gerolf F. Hoflehner, San Jose, CA (US);

Ethan Schuchman, San Jose, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); F01D 5/08 (2006.01); F02C 7/18 (2006.01); G06F 9/445 (2006.01);
U.S. Cl.
CPC ...
G06F 8/52 (2013.01); F01D 5/082 (2013.01); F02C 7/18 (2013.01); G06F 8/51 (2013.01); G06F 9/44589 (2013.01); F05D 2250/38 (2013.01); F05D 2260/14 (2013.01); F05D 2260/941 (2013.01); Y10T 29/49 (2015.01); Y10T 29/49995 (2015.01);
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to validate translated guest code in a dynamic binary translator. An example apparatus disclosed herein includes a translator to generate a first translation of code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine. The example apparatus also includes a translation versions manager to identify a first host machine state based on executing a portion of the first translation, and the translation versions manager to identify a second host machine state based on executing a portion of the second translation. The example system also includes a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state.


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