The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Jan. 19, 2012
Applicants:

Steven L. Kimbel, St. Charles, MO (US);

Jihong (John) Chen, St. Charles, MO (US);

Richard G. Schrenker, Chesterfield, MO (US);

Lee W. Ferry, St. Charles, MO (US);

Inventors:

Steven L. Kimbel, St. Charles, MO (US);

Jihong (John) Chen, St. Charles, MO (US);

Richard G. Schrenker, Chesterfield, MO (US);

Lee W. Ferry, St. Charles, MO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 11/02 (2006.01); C30B 11/00 (2006.01); C30B 28/06 (2006.01); C30B 29/06 (2006.01);
U.S. Cl.
CPC ...
C30B 11/002 (2013.01); C30B 11/02 (2013.01); C30B 28/06 (2013.01); C30B 29/06 (2013.01); Y10T 117/1092 (2015.01);
Abstract

A directional solidification furnace includes a crucible for holding molten silicon and a lid covering the crucible and forming an enclosure over the molten silicon. The crucible also includes an inlet in the lid for introducing inert gas above the molten silicon to inhibit contamination of the molten silicon.


Find Patent Forward Citations

Kimbel, Steven. (2015). Directional solidification furnace for reducing melt contamination and reducing wafer contamination (U.S. Patent No. 9222196). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9222196

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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