The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Jan. 31, 2014
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Hwong-Kwo Lin, Santa Clara, CA (US);

Ge Yang, Santa Clara, CA (US);

Xi Zhang, Santa Clara, CA (US);

Ying Huang, Santa Clara, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 19/003 (2006.01); H03K 3/037 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
H03K 19/003 (2013.01); G06F 1/10 (2013.01); H03K 3/0372 (2013.01);
Abstract

A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).


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