The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Jan. 08, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wen-Tai Chiang, Tainan, TW;

Chun-Hsien Lin, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 21/28518 (2013.01); H01L 21/76804 (2013.01); H01L 29/41725 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 21/76814 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.


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