The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Nov. 20, 2014
Applicant:

Samsung Electronics Co., Ltd, Suwon-si, KR;

Inventors:

Jaehun Jeong, Hwaseong-si, KR;

Hansoo Kim, Suwon-si, KR;

Jaehoon Jang, Seongnam-si, KR;

Hoosung Cho, Yongin-si, KR;

Kyoung-Hoon Kim, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11578 (2013.01); H01L 27/115 (2013.01); H01L 27/11517 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.


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