The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Feb. 05, 2013
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Deepak Thimmegowda, Boise, ID (US);

Brian Cleereman, Boise, ID (US);

Khaled Hasnat, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 29/417 (2006.01); H01L 27/115 (2006.01); H01L 27/02 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 27/0207 (2013.01); H01L 27/11519 (2013.01); H01L 29/7889 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01);
Abstract

A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.


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