The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Oct. 05, 2009
Applicants:

Eugene A. Fitzgerald, Windham, NH (US);

Nicole Gerrish, Santa Clara, CA (US);

Inventors:

Eugene A. Fitzgerald, Windham, NH (US);

Nicole Gerrish, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/823807 (2013.01); H01L 27/092 (2013.01); H01L 29/1054 (2013.01);
Abstract

A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.


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