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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9219056 B1

PDFFull Text
Expired
Date of Patent:
Dec. 22, 2015

Filed:

Mar. 27, 2012

Passive devices for finfet integrated circuit technologies

Applicants:

William F. Clark, Jr., Essex Junction, VT (US);

Robert J. Gauthier, Jr., Hinesburg, VT (US);

Junjun LI, Williston, VT (US);

Inventors:

William F. Clark, Jr., Essex Junction, VT (US);

Robert J. Gauthier, Jr., Hinesburg, VT (US);

Junjun Li, Williston, VT (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Thompson Hine LLP

Anthony J. Canale

Primary Examiner:

Julio J Maldonado

Assistant Examiner:

Damon Hillman

Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 21/20 (2006.01); H01L 21/33 (2006.01); H01L 27/02 (2006.01); H01L 21/8249 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 21/8249 (2013.01); H01L 21/845 (2013.01); H01L 27/06 (2013.01); H01L 27/1211 (2013.01); H01L 29/06 (2013.01);
Abstract

Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Find Patent Forward Citations

Clark, Jr., William. (2015). Passive devices for finfet integrated circuit technologies (U.S. Patent No. 9219056). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9219056

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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