The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2015
Filed:
Sep. 24, 2014
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Sampath Purushothaman, Yorktown Heights, NY (US);
Anna W. Topol, Jefferson Valley, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 21/02266 (2013.01); H01L 21/56 (2013.01); H01L 21/6835 (2013.01); H01L 23/3164 (2013.01); H01L 25/50 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/45147 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01015 (2013.01);
Abstract
A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.