The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

May. 15, 2012
Applicants:

Jozefus Godefridus Gerardus Pancratius Van Gisbergen, Hilvarenbeek, NL;

Daniel James Blakely, Yokohama, JP;

Rob Oomens, Eindhoven, NL;

Jacob Zelnik, Sunnyvale, CA (US);

Inventors:

Jozefus Godefridus Gerardus Pancratius Van Gisbergen, Hilvarenbeek, NL;

Daniel James Blakely, Yokohama, JP;

Rob Oomens, Eindhoven, NL;

Jacob Zelnik, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01);
Abstract

A method, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The methodcomprises the steps of: i) receivingthe integrated circuit layout, ii) receivinga drawing of the reference pattern from a user, iii) deductinga basic pattern definition from the drawn reference pattern, iv) determininga set of topological relation based on the drawn reference pattern, v) forminga complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checkingthe integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storingfound instances of the reference pattern.


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