The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Jan. 20, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Pratyush Kamal, San Diego, CA (US);

Yang Du, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/10 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 17/5081 (2013.01); G06F 17/5031 (2013.01); G06F 17/5068 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 2217/62 (2013.01); G06F 2217/84 (2013.01); H01L 27/0688 (2013.01);
Abstract

Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.


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