The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Jun. 30, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Georgios Palaskas, Portland, OR (US);

Paolo Madoglio, Beaverton, OR (US);

Stefano Pellerano, Beaverton, OR (US);

Ashoke Ravi, Hillsboro, OR (US);

Kailash Chandrashekar, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 7/06 (2006.01); H03C 3/00 (2006.01); H04L 27/12 (2006.01); H04L 7/00 (2006.01); H04B 17/21 (2015.01);
U.S. Cl.
CPC ...
H04L 7/0004 (2013.01); H04B 17/21 (2015.01); H04L 7/0087 (2013.01);
Abstract

This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.


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