The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9209275 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 08, 2015

Filed:

Jul. 29, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Zheng Zou, Singapore, SG;

Alex See, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 21/28273 (2013.01); H01L 21/28518 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/42336 (2013.01); H01L 29/4975 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01);
Abstract

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes removing a central plug from between a first memory cell and a second memory cell to define a center gap. Each of the first and second memory cells include a control gate with a control gate height, a cap overlying the control gate, a select gate adjacent to the control gate, and a select gate dielectric between the control gate and the select gate. The select gate is recessed to a select gate height while the cap overlies the control gate, where the select gate height is less than the control gate height. A memory spacer is formed overlying the select gate dielectric and adjacent to the control gate.


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