The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Aug. 18, 2014
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Marcello Mariani, Milan, IT;

Alessandro Grossi, Milan, IT;

Federica Zanderigo, Milan, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/74 (2006.01); H01L 27/105 (2006.01); H01L 21/8222 (2006.01); H01L 27/102 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01); G03F 7/20 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/105 (2013.01); G03F 7/20 (2013.01); H01L 21/30604 (2013.01); H01L 21/768 (2013.01); H01L 21/76224 (2013.01); H01L 21/8222 (2013.01); H01L 21/823412 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 27/1022 (2013.01); H01L 27/1027 (2013.01); H01L 29/4236 (2013.01); H01L 29/6656 (2013.01); H01L 29/66363 (2013.01);
Abstract

A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally from a substrate and spaced from one another along rows and columns. A gate line is formed laterally proximate each of two opposing sidewalls of the blocks along individual rows of the blocks. After forming the gate lines, semiconductor material of the blocks is removed laterally between the gate lines to form pairs of pillars from the individual blocks that individually have one of the gate lines laterally proximate one of two laterally outermost sidewalls of the pair and another of the gate lines laterally proximate the other of the two laterally outermost sidewalls of the pair. Other methods are disclosed.


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