The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
Sep. 29, 2014
Applicants:
Lee Fee Ngion, Melaka, MY;
Zi Song Poh, Melaka, MY;
Inventors:
Lee Fee Ngion, Melaka, MY;
Zi Song Poh, Melaka, MY;
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/14 (2006.01); H01L 21/78 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 21/4889 (2013.01); H01L 21/78 (2013.01); H01L 23/14 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 2224/0905 (2013.01); H01L 2224/0951 (2013.01);
Abstract
A substrate for use in semiconductor device assembly has an electrically insulating body with a die mounting surface and an opposite grid array surface. An array of external electrical connection pads is located in the grid array surface. Substrate bond padsare located in the die mounting surface. Interconnects in the insulating body selectively interconnect the substrate bond padsto the external electrical connection pads. Tertiary bond pads are located in the die mounting surface and are electrically isolated from the external electrical connection pads.