The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Mar. 24, 2014
Applicants:

Douglas R. Hackler, Sr., Boise, ID (US);

Dale G. Wilson, Kuna, ID (US);

Inventors:

Douglas R. Hackler, Sr., Boise, ID (US);

Dale G. Wilson, Kuna, ID (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); H01L 23/3135 (2013.01);
Abstract

This method of waferscale packaging produces finished integrated circuits (ICs) individually completely encapsulated with environmentally protective packaging material while still in the wafer format. Following conventional semiconductor fabrication of chips at the wafer level and prior to their separation, a first polymer is applied to the front surface of the wafer with allowance for contact holes. A carrier wafer is attached to the exposed polymer. The original substrate is removed and the devices are separated by cutting through the semiconductor layer and the first polymer. A second polymer is applied to cover the exposed backside of the devices and to fill the cut spaces between them, thereby sealing the remaining five surfaces of the chips. The second polymer layer may also include contact holes for access to the back side of the device chips. A second singulation cutting leaves the chips on the wafer prepared for a pick-and-place operation.


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