The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

May. 05, 2010
Applicants:

Xiaowei Deng, Plano, TX (US);

Wah K. Loh, Richardson, TX (US);

Inventors:

Xiaowei Deng, Plano, TX (US);

Wah K. Loh, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/48 (2006.01); G11C 29/54 (2006.01); G11C 29/50 (2006.01); G11C 29/12 (2006.01); G11C 11/416 (2006.01);
U.S. Cl.
CPC ...
G11C 29/48 (2013.01); G11C 29/54 (2013.01); G11C 11/416 (2013.01); G11C 29/12 (2013.01); G11C 29/50 (2013.01); G11C 29/50004 (2013.01); G11C 29/50016 (2013.01); G11C 2029/5002 (2013.01); G11C 2029/5004 (2013.01); G11C 2029/5006 (2013.01);
Abstract

An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.


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