The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Nov. 29, 2011
Applicants:

Robert J. Safranek, Portland, OR (US);

Robert G. Blankenship, Tacoma, WA (US);

Zhong-ning Cai, Lake Oswego, OR (US);

Inventors:

Robert J. Safranek, Portland, OR (US);

Robert G. Blankenship, Tacoma, WA (US);

Zhong-Ning Cai, Lake Oswego, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1663 (2013.01); G06F 13/16 (2013.01); G06F 13/40 (2013.01); G06F 13/4004 (2013.01); G06F 13/4022 (2013.01);
Abstract

Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets.


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