The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Dec. 14, 2012
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gerald K. Bartley, Rochester, MN (US);

Philip R. Germann, Oronoco, MN (US);

William P. Hovis, Rochester, MN (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); G01R 31/28 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); H01L 22/32 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); G01R 31/26 (2013.01); G01R 31/2898 (2013.01); H01L 24/13 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/1184 (2013.01); H01L 2224/11472 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/11906 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14051 (2013.01);
Abstract

A semiconductor chip may include a die having one or more circuits. The semiconductor chip may include a plurality of die bumps, each having a first geometry, a first vertical profile, and a first volume. The die bumps may be coupled to the die and in electrical communication with the one or more circuits. The semiconductor device may include a plurality of test bumps each having a second geometry, a second vertical profile, and the first volume. The test bumps may be coupled to the die and in electrical communication with the one or more circuits. The first geometry and the second geometry may be adapted for the plurality of test bumps to make connection with a wafer probe to the test bumps without making a connection to any of the die bumps during a die test.


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