The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Feb. 17, 2014
Applicants:

Chin-sheng Wang, Hsinchu County, TW;

Ching-sheng Chen, Hsinchu County, TW;

Chun-kai Lin, Hsinchu County, TW;

Chao-min Wang, Hsinchu County, TW;

Inventors:

Chin-Sheng Wang, Hsinchu County, TW;

Ching-Sheng Chen, Hsinchu County, TW;

Chun-Kai Lin, Hsinchu County, TW;

Chao-Min Wang, Hsinchu County, TW;

Assignee:

Subtron Technology Co., Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/40 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/113 (2013.01); H05K 3/4007 (2013.01); H05K 1/115 (2013.01); H05K 3/0097 (2013.01); H05K 2201/0376 (2013.01); H05K 2201/0959 (2013.01); H05K 2201/09509 (2013.01); H05K 2203/0152 (2013.01); H05K 2203/0156 (2013.01); H05K 2203/1536 (2013.01); H05K 2203/1563 (2013.01);
Abstract

A circuit board includes a circuit layer, a first solder resist layer, a second solder resist layer and at least one conductive bump. The first solder resist layer is disposed on a lower surface of the circuit layer and has at least one first opening exposing a portion of the lower surface of the circuit layer. The second solder resist layer is disposed on an upper surface of the circuit layer and has at least one second opening exposing a portion of the upper surface of the circuit layer. The conductive bump is disposed inside the second opening of the second solder resist layer and directly connects to the upper surface of the circuit layer exposed by the second opening. A top surface of the conductive bump is higher than a second surface of the second solder resist layer.


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