The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Dec. 31, 2013
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Lei Wang, Singapore, SG;

Lup San Leong, Singapore, SG;

Wei Lu, Singapore, SG;

Alex See, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76819 (2013.01); H01L 21/02164 (2013.01); H01L 21/02216 (2013.01); H01L 21/02274 (2013.01); H01L 21/76805 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01);
Abstract

Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.


Find Patent Forward Citations

Loading…