The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Mar. 13, 2013
Applicant:

Calypto Design Systems, Inc., San Jose, CA (US);

Inventors:

Nikhil Tripathi, Noida, IN;

Vishnu Kanwar, Faridabad, IN;

Manish Kumar, Indirapuram, IN;

Srihari Yechangunja, Bangalore, IN;

Assignee:

Calypto Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/504 (2013.01); G06F 17/505 (2013.01); G06F 17/5022 (2013.01); G06F 2217/78 (2013.01);
Abstract

Disclosed below are representative embodiments of methods, apparatus, and systems for performing power analysis during the design and verification of a circuit. Certain exemplary embodiments include user interfaces and software infrastructures that provide a flexible and powerful environment for performing power analysis. For example, embodiments of the disclosed technology can be used to construct complex and targeted power queries that quickly provide a designer with power information during a circuit design process. The disclosed methods can be implemented by a software tool (e.g., a power analysis tool or other EDA tool) that computes and reports power characteristics in a circuit design (e.g., a system-on-a-chip design or other integrated design).


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