The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Oct. 29, 2014
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano, JP;

Inventors:

Yuji Kunimoto, Nagano, JP;

Naoyuki Koizumi, Nagano, JP;

Assignee:

SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano-shi, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H05K 1/11 (2006.01); H01L 23/00 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H01L 23/498 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/112 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/17 (2013.01); H05K 1/0298 (2013.01); H05K 1/0306 (2013.01); H05K 1/0313 (2013.01); H01L 23/49816 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15788 (2013.01); H01L 2924/351 (2013.01); H05K 3/4605 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/025 (2013.01); Y10T 29/49155 (2015.01);
Abstract

A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.


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