The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Apr. 12, 2013
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Hua-Chou Tseng, Hsin-Chu, TW;
Han-Chung Lin, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 21/337 (2006.01); H01L 29/808 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 27/098 (2006.01);
U.S. Cl.
CPC ...
H01L 29/808 (2013.01); H01L 27/088 (2013.01); H01L 27/098 (2013.01); H01L 29/66901 (2013.01);
Abstract
A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments. The transistor channel is therefore accurately dimensioned.