The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Dec. 08, 2014
United Microelectronics Corp., Hsin-Chu, TW;
Kuan-Yu Chen, New Taipei, TW;
Tseng-Hsun Liu, Taipei, TW;
Min-Hsuan Tsai, Tainan, TW;
Te-Chang Chiu, Hsinchu County, TW;
Chiu-Ling Lee, Hsinchu, TW;
Chiu-Te Lee, Hsinchu County, TW;
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.